DFT Engineer

TL;DR

DFT Engineer (Chip Design): Developing and implementing chip-level Design for Test architectures with an accent on scan, BIST, and boundary scan. Focus on verifying DFT logic through simulation, performing static timing analysis, and debugging patterns on ATE.

Location: Shanghai, China

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Define chip-level DFT architecture.
• Implement core DFT schemes including scan, boundary scan, Mem BIST, and Logic BIST.
• Verify DFT logic and test patterns through simulation.
• Perform static timing analysis for test modes.
• Participate in ATE bring-up and debug DFT patterns on ATE.

Requirements

• Experience in DFT architecture definition and implementation.
• Proficiency with Mem BIST, Logic BIST, and boundary scan.
• Ability to perform simulation and static timing analysis (STA).
• Experience with ATE bring-up and pattern debugging.
• Must be located in or able to work from Shanghai, China