Senior Staff Verification Engineer (PCIe & Memory Subsystems)

TL;DR

Senior Staff Verification Engineer (PCIe & Memory Subsystems): Architecting and developing functional verification environments for high-performance data processing silicon platforms with an accent on PCIe and memory subsystems. Focus on creating scalable testbench architectures using UVM and SystemVerilog and solving complex SOC-level verification challenges.

Location: Santa Clara, CA (Must be eligible to access export-controlled information under U.S. law)

Salary: $134,390 – $201,300 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Architect and develop functional verification environments, including reference models, bus-functional monitors, and drivers.
• Write comprehensive verification test plans employing random techniques, directed testing, and coverage analysis.
• Develop testbenches utilizing UVM, SystemVerilog, C/C++, and DPI.
• Execute verification at block, unit, subsystem, and SOC levels.
• Collaborate closely with logic designers to debug simulation failures and resolve functional issues.

Requirements

• BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering.
• 5-10 years of professional experience in SOC verification and testbench development.
• Expertise in UVM, SystemVerilog, object-oriented programming, and constrained random methods.
• Experience with EDA verification tools, scripting languages (Python or Perl), and revision control systems.
• Must be eligible to access export-controlled information (U.S. citizen, lawful permanent resident, or protected individual).

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate professional milestones.