ASIC Design Verification Engineer (SystemVerilog/UVM)

Location: Irvine, California, USA; onsite

Annual base salary: $129,400–$207,000, plus eligibility for a discretionary annual bonus and equity.

Company

hirify.global develops silicon products and high-throughput Ethernet solutions for cloud systems and AI/ML workflows.

What you will do

• Develop verification environments for new ASIC designs used in Ethernet systems.
• Apply constrained-random verification methodologies and drive completion through coverage closure.
• Build SystemVerilog testbench structures using classes, assertions, and related constructs.
• Use UVM and industry-standard verification tools, including VCS and Incisive.
• Collaborate with worldwide design and architecture teams on leading-edge products.
• Participate in all aspects of design verification, with opportunities for technical leadership.

Requirements

• Bachelor’s degree with 12+ years of related experience, Master’s degree with 10+ years, or PhD with 3+ years.
• Experience with constrained-random verification methodologies and coverage closure.
• Strong SystemVerilog and UVM experience, including object-oriented programming.
• Experience with SystemVerilog testbench structures, classes, and SVA.
• Ability to work effectively in a collaborative engineering environment.

Nice to have

• Scripting experience with Python, Perl, or similar languages.

Culture & Benefits

• Stable engineering team focused on rapidly evolving Ethernet products.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Paid holidays, sick leave, vacation time, and applicable family and other leaves.
• Employee Assistance Program and eligibility for bonus and equity programs.