ASIC Design Verification Engineer (AI)

TL;DR

ASIC Design Verification Engineer (AI): Developing silicon products for Ethernet systems in the Cloud with an accent on constrained random verification methodologies. Focus on verifying high-throughput Ethernet solutions that accelerate AI/ML workflows using SystemVerilog and UVM.

Location: Must be based in Irvine, CA, USA

Salary: $129,400–$207,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Verify new silicon designs for high-throughput Ethernet systems.
• Apply constrained random verification methodologies to ensure design quality.
• Drive completion via coverage closure.
• Collaborate with worldwide design and architecture teams.
• Develop and maintain testbench structures using SystemVerilog and UVM.
• Provide technical leadership within the verification group.

Requirements

• Must be based in or able to work from Irvine, CA
• 12+ years of experience with a Bachelor's degree, 10+ years with a Master's, or 3+ years with a PhD.
• Strong expertise in constrained random verification methodologies.
• Proficiency in SystemVerilog and UVM.
• Solid understanding of OOP principles.
• Strong teamwork and communication skills.

Nice to have

• Scripting skills in Python or Perl.
• Experience with VCS or Incisive tools.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Discretionary annual bonus eligibility.
• Paid holidays, sick leave, and vacation time.