ASIC Implementation Engineer (AI)

TL;DR

ASIC Implementation Engineer (AI): Leading top-level floorplanning and physical design for next-generation AI and PCIe switch products with an accent on RTL-to-silicon tape-out. Focus on chip floor planning, partition creation, clock tree delivery, and resolving complex physical design issues for advanced nodes.

Location: Must work in person at our San Jose site; no remote work option.

Salary: $143,800 - $230,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Own chip floor planning, partition creation, and clock tree delivery for top-level partitions.
• Resolve physical design issues related to chip integration and assembly.
• Manage cross-functional interactions regarding floorplanning, I/O, and bump planning with the package team.
• Develop and improve floorplan implementation methodologies using industry and internal tools.
• Perform technical evaluations of vendors and IP to meet design specifications.

Requirements

• Must work in person at our San Jose site.
• Bachelors in Electrical Engineering with 12+ years or Master's with 10+ years of experience in top-level floorplanning.
• Expertise in die size estimation, partitioning, clocking, and pin planning.
• Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
• Experience resolving chip-level DRC/LVS/EMIR issues for advanced nodes.
• Proficiency in scripting languages like Python, Tcl, or Perl and EDA tools.

Culture & Benefits

• Competitive base salary with discretionary annual bonus and equity awards.
• Comprehensive benefits package including medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Paid holidays, sick leave, and vacation time.