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5 дней назад

Principal RTL Design Engineer (AI)

180 000 - 255 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Principal RTL Design Engineer (AI): Designing and integrating high-speed IO and memory subsystems for SambaNova's DataScale AI platform with an accent on SystemVerilog RTL, ASIC microarchitecture, and PPA optimization. Focus on PCIe, Ethernet, CXL, HBM, and die-to-die integration, front-end design flows, timing closure, and resolving complex functional and performance issues.

Location: Austin, Texas, United States, or San Jose, California, United States

Salary: $180,000–$255,000 USD base salary

Company

hirify.global develops full-stack AI infrastructure centered on its Reconfigurable Dataflow Unit (RDU) and rack-scale SambaRack systems for high-performance inference.

What you will do

  • Define architecture, feasibility studies, trade-offs, and microarchitecture for high-speed IO and memory subsystems.
  • Design synthesizable SystemVerilog RTL and integrate internal and third-party IP across the product lifecycle.
  • Run front-end design flows, including lint, CDC/RDC, synthesis, timing constraints, and design-for-test readiness.
  • Partner with STA and physical design teams on timing closure, floorplanning, congestion analysis, and optimization at advanced process nodes.
  • Collaborate with verification, emulation, software, and firmware teams to validate designs and deliver end-to-end solutions.
  • Lead cross-functional triage of functional and performance issues and improve design, integration, and flow scalability.

Requirements

  • MS in Electrical Engineering, Computer Science, or a related field.
  • 7+ years of ASIC design experience, including logic design, microarchitecture, specifications, SystemVerilog RTL, and functional verification.
  • Experience optimizing power, performance, or area and delivering designs against functional and performance targets.
  • Experience with at least two on-chip or chip-to-chip protocols, such as AXI, APB, PCIe, Ethernet, or UCIe.
  • Experience with memory subsystems such as HBM and CXL, including evaluating vendor IP and interpreting complex protocol specifications.
  • Clear communication skills and a proactive, collaborative approach to problem-solving.

Nice to have

  • Experience taking ASIC products from concept to silicon.
  • Familiarity with ESUN, SUE, UAL, or Ultra Ethernet protocols.
  • Experience with NoC fabrics, switches, arbiters, traffic management, quality-of-service, or congestion control.
  • Knowledge of machine learning and hardware accelerator architectures.

Culture & Benefits

  • Full-time US employment with base salary, equity, and benefits.
  • Medical insurance covering 95% of employee premiums and 77% of dependent premiums.
  • Health Savings Account with employer contribution, plus dental, vision, disability, life, AD&D, and Flexible Spending Account options.
  • Well-being benefits including Headspace, Gympass+, One Medical, and counseling services.

Hiring process

  • Submit a separate application form for each position for which you are qualified.

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