4 дня назад
Senior Design Verification Engineer (Digital)
130 000 - 200 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Design Verification Engineer (Digital) (SystemVerilog/UVM): Developing verification plans, testbenches, and coverage strategies for digital IP blocks, subsystems, and full-chip mixed-signal sensing products with an accent on constrained-random verification, RTL and gate-level simulation, and cross-functional hardware integration. Focus on debugging complex failures, driving coverage closure, mentoring verification engineers, and supporting silicon validation, production test, and application engineering.
Location: San Diego, California, USA; hybrid
Salary: $130,000–$200,000 per year
Company
supplies analog and mixed-signal semiconductors for consumer, computing, communications, and industrial equipment, including low-power sensing products for touch and proximity applications.
What you will do
- Define and optimize verification plans, test strategies, coverage models, and verification environments for digital IP blocks, subsystems, and full integrated circuits.
- Design and implement SystemVerilog UVM testbenches for block-level and full-chip RTL and gate-level verification.
- Develop constrained-random and directed tests, reusable verification components, regression infrastructure, continuous integration flows, and coverage tracking.
- Debug simulation failures, identify RTL and verification root causes, and improve verification scalability and reuse.
- Collaborate with system, digital, physical design, firmware, analog, test, product, and application engineering teams.
- Mentor junior verification engineers and support silicon evaluation, performance characterization, and debug.
Requirements
- 8+ years of industry experience in integrated circuit design verification.
- In-depth experience verifying digital logic in mixed-signal ICs with MCU-based systems, memories, interfaces, peripherals, embedded signal processing, external IP, and analog peripherals.
- Strong SystemVerilog and UVM skills, Verilog RTL and gate-level debug experience, Python scripting, and familiarity with VCS, Xcelium, or Questa.
- Experience with I2C, I3C, SPI, or MIPI hardware protocols.
- Technical leadership, analytical and problem-solving skills, and strong written and verbal communication.
- B.S. or M.S. degree in Electrical or Computer Engineering.
Nice to have
- Experience with analog behavioral models, formal verification, CDC/RDC sign-off, low-power verification with UPF/CPF, and lint or structural sign-off.
- Knowledge of system-level integration, embedded firmware, and signal processing.
- Experience with capacitive sensing, touch, or proximity ICs.
Culture & Benefits
- Collaborative work across system, hardware, firmware, analog, test, product, and application engineering functions.
- Technical leadership and mentoring responsibilities.
- Hybrid work based in the San Diego office.
- Equal employment opportunity and a drug-free workplace.
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