Staff Design Verification Engineer – CPU Core Verification (Vector)

Location: Austin, Texas, United States. Requires proof of the right to work in the United States and authorization to access export-controlled technology.

Compensation includes base pay with potential variable or incentive compensation and/or equity.

Company

hirify.global develops high-performance RISC-V compute platforms for applications including AI, machine learning, automotive, data center, mobile, and consumer technologies.

What you will do

• Own verification planning and execution for high-performance out-of-order CPU core areas from block level through integration and signoff.
• Drive verification strategy, test planning, debugging, coverage analysis, and closure for complex microarchitectural interactions.
• Verify RISC-V Vector Extension functionality, including vector arithmetic, memory operations, masking, configuration-dependent execution, exceptions, and scalar-vector interactions.
• Develop verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Partner with architecture, RTL, performance, compiler, system verification, and software teams to resolve specification and verification gaps.
• Improve reusable verification methodology and infrastructure while mentoring other engineers.

Requirements

• Must be authorized to work in the United States and satisfy export-control access requirements.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• At least 7 years of relevant ASIC, CPU/core, or SoC design verification experience, with ownership of complex verification problems.
• Strong hands-on experience with SystemVerilog-based verification, modern verification methodologies, CPU verification, and computer architecture.
• Experience with CPU areas such as frontend, midcore, load-store units, memory ordering, hardware prefetch, or vector units.
• Programming or scripting experience with Python, C, C++, or similar languages, plus strong debugging and coverage-closure skills.

Nice to have

• Experience with high-performance out-of-order CPU verification and RISC-V Vector Extension, SIMD, or vector processors.
• Experience verifying vector memory behavior, configuration modes such as SEW, LMUL, VL, and VSTART, and complex concurrency or weak-memory-ordering scenarios.
• Experience with formal verification, emulation, acceleration, assertions, checkers, and scoreboards.

Culture & Benefits

• Collaborative work across architecture, design, performance, verification, compiler, system verification, and software teams.
• Opportunity to contribute to high-performance out-of-order CPU core programs implementing the latest RVV.
• Competitive benefits package that may include healthcare, retirement plans, and paid time off.
• Potential variable or incentive compensation and/or equity.