Senior Staff Design Engineer - Memory Subsystem COE (Semiconductor)

Location: San Diego, California, United States

Salary: $135,900–$201,130 per year

Company

hirify.global develops semiconductor solutions and reusable IP subsystems for enterprise, cloud, AI, carrier, and data center architectures.

What you will do

• Define the micro-architecture, implement RTL, and integrate DDR, LPDDR, and HBM subsystems.
• Translate architecture requirements into robust RTL designs and collaborate with architecture teams.
• Review verification test plans, debug issues, and drive coverage closure with Design Verification teams.
• Partner with Physical Design and DFT teams to deliver PD-friendly and DFT-ready RTL.
• Support silicon bring-up and post-silicon debug with firmware and validation teams.
• Improve design quality, coding practices, reuse, and provide technical leadership and mentoring.

Requirements

• Bachelor’s degree in Electronics or Electrical Engineering with 5–10+ years of relevant experience, or a Master’s and/or PhD with 3–5 years of relevant experience.
• Experience delivering complex DDR, LPDDR, HBM controllers, or subsystems from architecture through RTL closure and sign-off.
• Strong hands-on SystemVerilog and Verilog RTL development experience.
• Knowledge of DDR/HBM JEDEC specifications, ARM-based SoC integration, and AMBA protocols including AXI-4, CHI, and ACE.
• Understanding of clocking, resets, CDC/RDC, low-power techniques, performance optimization, lint, synthesis, and design sign-off flows.
• Experience with Synopsys, Cadence, or Mentor/Siemens EDA tools; scripting with TCL, Perl, or Python; and version control systems such as Git or SVN.

Culture & Benefits

• Work within a cross-functional Center of Excellence serving multiple SoC business units.
• Contribute to reusable, production-ready IP designed to reduce integration risk and improve time-to-market.
• Employee stock purchase plan with a two-year look-back.
• Family support programs, mental health resources, and physical health benefits.
• Recognition and service awards for contributions and milestones.

Hiring process

• Interviews assess individual experience, technical reasoning, and communication skills.
• AI tools, transcription applications, real-time answer generators, and automated note-taking bots are prohibited during interviews.
• Access to export-controlled technology may require an export license review before employment.