DFT Design Engineer (ASIC)

TL;DR

DFT Design Engineer (ASIC): Designing and implementing Design for Test (DFT) architectures for SoC/ASIC with an accent on scan chain insertion, compression technologies, and ATPG pattern generation. Focus on improving fault coverage, verifying testbenches, and implementing MBIST and JTAG standards to ensure hardware reliability.

Location: Austin, TX. US citizenship preferred.

Company

hirify.global is a leading provider of electronic design automation (EDA) software and hardware tools for chip design.

What you will do

• Implement scan chain insertion, compression scan technologies, and memory built-in self-test (MBIST).
• Develop and execute Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals.
• Perform debug and analysis of failures to optimize fault coverage and identify root causes of simulation mis-compares.
• Verify ATPG testbenches and ensure design quality metrics are met.
• Utilize JTAG 1149.1/6, IEEE1500, and IEEE1687 standards in the design process.
• Collaborate with cross-functional teams, including Architecture and Design stakeholders.

Requirements

• 3-12 years of professional experience in SoC/ASIC Digital Design with a focus on DFT.
• Deep knowledge of DFT insertion flows, LBIST, and MBIST.
• Expertise in ATPG and failure analysis to improve fault coverage.
• Hands-on experience with synthesis, verification, and debugging Verilog testbenches.
• Working knowledge of JTAG 1149.1/6, IEEE1500, and IEEE1687.
• US citizenship preferred.

Nice to have

• Prior experience with hirify.global tools and flows.
• Knowledge of timing analysis and equivalency checks.