Design For Test Engineer III (Semiconductors)

TL;DR

Design For Test Engineer III (Semiconductors): Implementing DFT for 3nm and 5nm networking chips with an accent on scan-insertion, ATPG pattern generation, and MBIST verification. Focus on optimizing DFT flows through scripting in Perl, Shell, and TCL, and performing silicon debug and bring-up for high-gate-count SoCs.

Location: Fully On-Site in San Jose, CA

Salary: $95,900 - $170,500

Company

A leading global provider of product engineering and semiconductor design services, part of hirify.global (Fortune #109).

What you will do

• Implement DFT for 3nm and 5nm Networking chips and IP DFT work.
• Perform RTL checks for scan-insertion compatibility using Synopsys Spyglass.
• Execute Scan-Insertion using Tessent TestKompress and ATPG pattern generation.
• Conduct pattern simulation (with and without timing) using VCS and debug mismatches with Verdi.
• Automate and enhance DFT flows using Perl, Shell, and TCL scripts.
• Handle MBIST insertion, verification, and IEEE 1149.1 JTAG implementation and silicon bring-up.

Requirements

• 5–7 years of experience in DFT.
• Proficiency in Scan-Insertion, ATPG, GLS, and Pattern Simulations.
• Experience with MBIST and IEEE 1149.1 JTAG insertion and verification.
• Strong scripting skills in Perl, Shell, and TCL.
• Experience with multi-million gate count SoCs (Networking, Consumer, PLL, Serdes).
• Degree (B.Tech/M.Tech) in Microelectronics or Electronics.
• Must be able to work fully on-site in San Jose, CA.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance.
• 401k plan with matching contributions.
• Health Savings Account (HSA) and Health Reimbursement Account (HRA) options.
• Paid Time Off and tuition reimbursement.
• Short-term and long-term disability insurance.
• Professional growth opportunities within a global engineering environment.