DFT Engineer (Semiconductor)

Location: Austin, Texas, USA — River Place B7; onsite role

Annual base salary: USD 109,700–175,500, plus discretionary annual bonus and equity awards.

Company

hirify.global develops semiconductor and connectivity technologies.

What you will do

• Implement DFT at block and chip level, including DFT lint checking, MBIST architecture, logic insertion, and scan insertion.
• Develop and simulate ATPG patterns for MBIST and scan testing.
• Develop ATE patterns, manage handoffs, and perform silicon debugging.
• Collaborate with ATE engineering on yield improvement and analysis.
• Work with design, verification, implementation, ATE, and product development teams throughout DFT design and silicon bring-up.
• Contribute to improvements in DFT design methodology.

Requirements

• Bachelor's degree in Engineering and 8+ years of related experience, or a Master's degree and 6+ years of related experience.
• Experience with silicon bring-up and yield improvement.
• Strong knowledge of DFT techniques, digital logic fundamentals, RTL lint checking, scan compression, scan insertion, and ATPG.
• Experience with MBIST architecture and insertion, simulation failure analysis, and debugging.
• Strong knowledge of Mentor Tessent, Synopsys DFT, and simulation tool suites.
• Proficiency in Perl or other scripting languages, along with strong communication and interpersonal skills.

Nice to have

• Experience developing STA constraints for DFT modes.

Culture & Benefits

• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program and Employee Assistance Program.
• Paid holidays, sick leave, vacation time, and applicable family and other leave.
• Discretionary annual bonus, competitive new-hire equity grant, and annual equity awards.