Quality Reliability Engineer (Semiconductor)

TL;DR

Quality Reliability Engineer (Semiconductor): Ensuring the quality, robustness, and long-term reliability of advanced semiconductor packages and board-level products with an accent on qualification planning, failure analysis, and reliability statistics. Focus on developing complex reliability strategies, investigating thermo-mechanical failure mechanisms, and influencing JEDEC and other industry standards.

Location: Onsite in Phoenix, Arizona, United States

Salary: $120,860–$170,630 USD annually

Company

hirify.global develops advanced semiconductor technologies, processors, and electronic systems.

What you will do

• Develop qualification plans for thermal cycling, mechanical shock, vibration, drop, power cycling, humidity, and use-condition testing.
• Establish reliability requirements, acceptance criteria, demonstration plans, and statistical confidence strategies.
• Lead FMEA, fault tree analysis, reliability growth, failure analysis, and root-cause investigations.
• Drive corrective and preventive actions across product design, materials, assembly, and manufacturing processes.
• Perform Weibull analysis, DOE studies, and reliability data analysis.
• Represent hirify.global in JEDEC, IPC, AEC, and related standards organizations, including JEDEC JC-14 committees.

Requirements

• Master’s degree in Materials Science, Mechanical Engineering, Electrical Engineering, Reliability Engineering, Physics, or a related technical field with 3+ years of industry experience, or a Ph.D. with 1+ years of industry experience.
• Experience in semiconductor package, board-level, or electronic system reliability.
• Knowledge of reliability qualification methods, accelerated stress testing, solder interconnect reliability, PCB technologies, SMT assembly, and package-to-board interactions.
• Experience supporting failure analysis, root-cause determination, FMEA, risk assessment, and qualification planning.
• Familiarity with JEDEC reliability standards and the ability to communicate technical findings through reports and technical discussions.
• Onsite presence in Phoenix, Arizona, United States is required.

Nice to have

• Experience with FCBGA, flip-chip, heterogeneous integration, chiplet-based architectures, or 2.5D/3D packaging.
• Knowledge of solder fatigue, pad cratering, substrate cracking, delamination, warpage, FEM, or physics-of-failure approaches.
• Prior participation in JEDEC, IPC, or similar standards activities.

Culture & Benefits

• Cross-functional collaboration with design, process, manufacturing, quality, supplier engineering, and customer organizations.
• Competitive compensation with stock bonuses.
• Health, retirement, and vacation benefits.
• Opportunities to contribute to industry standards, technical publications, and qualification methodologies.