Senior ASIC Design Verification Engineer (Space)

TL;DR

Senior ASIC Design Verification Engineer (Space): Verifying the functionality, performance, and robustness of custom silicon designs for high-power satellite platforms with an accent on SystemVerilog/UVM testbench development and coverage closure. Focus on driving constrained-random testing strategies, managing CI pipelines, and collaborating across architecture and physical design teams to ensure end-to-end silicon reliability.

Location: Must be based in Seattle, WA (Onsite). Role requires ITAR compliance, meaning candidates must be U.S. Persons (U.S. citizens, permanent residents, or protected individuals).

Salary: $170,000 – $250,000 + equity

Company

A Series C space startup building high-power satellite platforms for missions ranging from LEO to deep space.

What you will do

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM testbenches including agents, monitors, scoreboards, and coverage models.
• Drive constrained-random and directed testing strategies to validate functionality and stress scenarios.
• Implement and maintain functional, code, and assertion coverage to ensure sign-off.
• Manage regression testing, simulation farms, and CI pipelines for fast debug iterations.
• Collaborate with architecture, RTL, DFT, and physical design teams to influence design-for-verification practices.

Requirements

• U.S. Person status required for ITAR compliance.
• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
• Proficiency with simulation tools (VCS, Xcelium, Questa), waveform debug, and scripting (Python, Perl, TCL).
• Experience with UVM-based testbench development, regression management, and CI/CD automation.

Nice to have

• Experience developing and integrating reference models.
• Understanding of low power verification and gate-level simulation.
• Familiarity with post-silicon validation planning.
• Experience in space, telecom, or RF/digital mixed systems.

Culture & Benefits

• Equity in the company.
• Comprehensive medical, dental, and vision coverage.
• Paid time off and paid parental leave.
• Life insurance and other perks.
• Fast-paced environment working on groundbreaking space technology.