обновлено 17 дней назад
Principal ASIC Design Verification Engineer
190 000 - 285 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Principal ASIC Design Verification Engineer (SystemVerilog/UVM): Building verification environments for custom silicon used in high-power satellites with an accent on block-, subsystem-, and full-chip verification, coverage closure, and silicon validation. Focus on developing constrained-random and formal verification strategies, managing regressions and CI pipelines, and solving complex debug challenges across RTL, firmware, DFT, and physical design.
Location: United States - Remote. The role requires a U.S. person under ITAR regulations or eligibility for a federally issued export control license.
Salary: $190,000–$285,000 base salary per year, plus equity.
Company
develops high-power satellite platforms for commercial and U.S. government missions across multiple orbits.
What you will do
- Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
- Build SystemVerilog and UVM testbenches with agents, monitors, scoreboards, checkers, and coverage models.
- Develop assertions, integrate formal verification, and drive constrained-random and directed testing.
- Run simulations and regressions, debug failures, perform root-cause analysis, and achieve coverage closure.
- Manage simulation farms and CI pipelines while advancing design-for-verification methodologies.
- Collaborate with architecture, RTL, DFT, firmware, physical design, and silicon validation engineers; support silicon bring-up and post-silicon validation.
Requirements
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of experience in ASIC or SoC verification.
- Strong knowledge of SystemVerilog, digital logic, RTL design, DFT, and hardware verification flows.
- Experience with UVM, constrained-random testing, functional and code coverage, SystemVerilog assertions, regression management, and gate-level simulation.
- Proficiency with simulation and debug tools such as VCS, Xcelium, Questa, Verdi, or SimVision, plus scripting in Python, Perl, or TCL.
- Experience with reference models, embedded processor-based designs, firmware or bare-metal coding, standard interfaces such as APB, AHB, or AXI, and post-silicon validation.
Nice to have
- Experience with low-power verification, analog behavioral models, or physical design flows.
- Experience working in cross-functional, geographically distributed teams.
- Experience with space, telecom, or RF/digital mixed systems.
Culture & Benefits
- High-ownership, hands-on role shaping first-generation silicon.
- Opportunity to work on high-power satellite platforms and complex spacecraft systems.
- Comprehensive benefits including paid time off, medical, dental and vision coverage, life insurance, and paid parental leave.
- Equity participation is included in the compensation package.
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