Principal ASIC Design Verification Engineer

TL;DR

Principal ASIC Design Verification Engineer (ASIC/DV): Verify the functionality, performance, and robustness of custom silicon designs by defining verification approach, building SystemVerilog/UVM testbenches, and driving constrained-random, directed, and formal verification. Focus on coverage closure, simulation/regression throughput, failure triage with root-cause analysis, and shaping first-generation silicon through cross-functional DV and design-for-verification (DFV) collaboration.

Location: Seattle, WA

Salary: $190,000–$285,000 + equity

Company

hirify.global builds high-power satellite platforms for missions from LEO to deep space.

What you will do

• Develop and execute verification plans for block, subsystem, and full-chip environments.
• Build SystemVerilog/UVM testbenches (agents, monitors, scoreboards, checkers) and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing to validate functionality, corner cases, and stress scenarios; run simulations and triage failures with root-cause analysis.
• Implement and maintain functional/coverage closure (functional, code, assertion coverage) for sign-off.
• Manage regression testing, simulation farms, and CI pipelines; support silicon bring-up and post-silicon validation; lead complex systems and DV methodology improvements.

Requirements

• 10+ years of experience in ASIC/SoC verification.
• Strong SystemVerilog skills plus understanding of RTL design, DFT, and hardware design/verification flows.
• Experience with UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Proficiency with simulation and debug/coverage tools (VCS, Xcelium, Questa; Verdi, SimVision) and scripting (Python, Perl, TCL).
• Experience with regression management, coverage analysis, Git, CI/CD automation, and gate-level simulation.
• Experience with reference models and post-silicon validation planning/execution; embedded processor-based designs and firmware/bare-metal coding (C/C++) are required.

Nice to have

• Low power verification experience.
• Analog behavioral models experience.
• Familiarity with physical design flows.
• Experience in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems.

Culture & Benefits

• Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, and paid parental leave.
• Equity included in compensation.
• Hands-on role with high ownership and deep technical engagement.
• Opportunity to shape first-generation silicon and influence DV methodologies.

Hiring process

• ASIC team interviews as part of the selection process.
• Evaluation based on verification depth, tooling, and ability to drive complex DV execution and coverage closure.