RTL Integration Engineer (SystemVerilog)

Location: San Jose, California, USA

Salary: USD 143,800–230,000 annual base salary

Company

hirify.global is a technology corporation offering semiconductor and infrastructure software solutions.

What you will do

• Integrate IP and verify IP test and debug modes at the SoC level.
• Create RTL designs and perform linting.
• Execute CDC and RDC analysis for RTL and gate-level designs.
• Support synthesis, Palladium modeling, and static timing analysis.
• Debug zero-delay, SDF, and gate-level simulation failures.

Requirements

• Bachelor’s degree and 12+ years of related experience.
• Extensive knowledge of implementation, synthesis, and timing issues.
• Strong understanding of UVM and SystemVerilog.
• Experience with zero-delay and SDF simulations, gate-level simulation, and CDC analysis.
• Strong debugging, communication, independent-working, and adaptability skills.
• Experience working within a global team and dynamic environment.

Nice to have

• Experience with NCSim and VCS simulation tools.

Culture & Benefits

• Full-time employment with a discretionary annual bonus and equity awards.
• Medical, dental, and vision insurance.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Paid holidays, sick leave, vacation, and applicable family and other statutory leave.
• Employee Assistance Program.