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4 дня назад

Analog ASIC Design Engineer (RF)

148 900 - 276 500$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR

Analog ASIC Design Engineer (RF): Designing innovative CMOS, BiCMOS, and HBT RF integrated circuits for next-generation measurement products with an accent on circuit simulation, signal analysis, and system-level performance optimization. Focus on developing robust analog and mixed-signal building blocks while collaborating with cross-functional teams to drive architectural design decisions.

Location: Must be based in or able to work from Louisville, CO or Beaverton, OR.

Salary: $148,900–$276,500

Company

hirify.global, a subsidiary of Ralliant Corporation, is a global leader in precision-engineered measurement solutions, dedicated to pushing the boundaries of technology and innovation.

What you will do

  • Design and develop key analog and mixed-signal building blocks for next-generation ASICs.
  • Perform circuit simulations to optimize performance, robustness, and manufacturability.
  • Conduct signal and system-level analysis to ensure end-to-end performance.
  • Characterize designs and develop comprehensive characterization plans.
  • Partner with product line architects to evaluate power, cost, and performance trade-offs.
  • Contribute to technical documentation and design reviews throughout the development lifecycle.

Requirements

  • Must be a U.S. Person (U.S. Citizen or Green Card holder) due to ITAR/export control regulations.
  • BSEE or MSEE in Electrical Engineering.
  • 5+ years of hands-on experience designing analog and/or mixed-signal integrated circuits.
  • Proficiency with modern ASIC design and verification tools.
  • Strong foundation in analog and RF analysis prior to simulation.
  • Experience with layout of critical analog/RF cells.

Nice to have

  • MSEE or PhD in Electrical Engineering.
  • 10+ years of experience in analog and/or mixed-signal IC design.
  • Experience designing and optimizing PLL architectures.
  • Experience with 3D electromagnetic field solvers like Ansys HFSS or Cadence EMX.
  • Experience correlating silicon results with simulation in the lab.

Culture & Benefits

  • Inclusive engineering culture focused on continuous learning and growth.
  • Opportunity to work on mission-critical advancements across diverse industries.
  • Comprehensive compensation package including bonus eligibility.
  • Commitment to diversity, equity, and inclusion through the We Are More Together vision.
  • Supportive environment for professional development and solving complex technical challenges.

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