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21 час назад

Principal Analog Mixed-Signal Design Engineer (AI Infrastructure)

170 000 - 210 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Principal Analog Mixed-Signal Design Engineer (AI Infrastructure): Architecting and designing high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O connectivity in rack-scale AI infrastructure with an accent on PLLs, LDOs, data converters, clocking, and advanced FinFET processes. Focus on taking designs from architecture through silicon bring-up, characterization, and debug while setting design methodologies and mentoring engineers.

Location: Irvine, California, United States

Salary: $170,000–$210,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may also apply.

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

  • Architect and design high-speed analog and mixed-signal circuits, including PLLs, LDOs, references, SerDes building blocks, ADCs, DACs, and clocking circuits.
  • Drive circuit development from specifications and architecture through schematic design, layout supervision, and verification across PVT corners.
  • Develop robust designs in advanced FinFET process nodes while balancing power, area, and performance.
  • Lead silicon bring-up, characterization, debugging, and root-cause analysis with validation and product engineering teams.
  • Define test plans and correlate silicon performance with design targets.
  • Set analog design methodologies and review standards, collaborate across engineering functions, and mentor engineers.

Requirements

  • MS or PhD in Electrical Engineering or a related field.
  • 8+ years of experience in analog and mixed-signal integrated circuit design.
  • Track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS or FinFET nodes.
  • Strong understanding of physical-layer design, signal integrity, and high-speed I/O.
  • Proficiency with industry-standard design and simulation tools such as Cadence Virtuoso and Spectre.
  • Strong layout and parasitic-aware design skills.

Nice to have

  • Experience taking multiple analog or mixed-signal designs through production tape-out and high-volume manufacturing.
  • Expertise in PCIe, Ethernet, UALink, UCIe, and related PHY architectures.
  • Experience with silicon debug, ATE test development, design-for-test techniques, mentoring, and technical design reviews.
  • Excellent communication skills and a collaborative, ownership-driven mindset.

Culture & Benefits

  • High-impact, hands-on work supporting AI connectivity and advanced data-center infrastructure.
  • Opportunity to influence analog design methodology and technical standards.
  • Collaboration with digital, physical design, systems, architecture, validation, and product engineering teams.
  • Discretionary bonus, incentives, and benefits may be available.
  • Commitment to diverse ideas, backgrounds, and experiences.

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