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6 дней назад

Senior Technical Staff Engineer - Analog Design (SRAM Design)

91 000 - 232 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Technical Staff Engineer - Analog Design (SRAM Design) (SRAM/Analog Design): Designing complex, multiport SRAM blocks for advanced and low-power FPGA devices with an accent on speed, power, area, reliability, and programmable features. Focus on full-custom circuit design, SPICE and Verilog modeling, memory architecture, yield and variation analysis, and silicon validation.

Location: San Jose, California, United States; onsite role

Annual base salary: $91,000–$232,000

Company

hirify.global develops embedded control, FPGA, memory, mixed-signal, power management, connectivity, and other semiconductor products.

What you will do

  • Design and optimize full-custom, high-speed multiport SRAM blocks for advanced and low-power FPGA devices.
  • Define memory-array architecture for redundancy, ECC compliance, yield, speed, power, and area targets.
  • Create and verify circuit schematics and functional Verilog models, and compare simulations with SPICE-based models.
  • Simulate SRAM stability, read and write margins, retention, noise margins, critical paths, and functional features.
  • Develop sense amplifiers, testability circuitry, and low-power memory techniques.
  • Collaborate with architecture, ASIC, firmware, verification, timing, test, layout, and software-model teams through characterization and silicon validation.

Requirements

  • Bachelor’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
  • 12+ years of experience in custom SRAM or memory-circuit design.
  • High proficiency with SPICE simulation and full-custom EDA tools.
  • Experience with scripting, simulation-queue management, data capture, and analysis.
  • Ability to analyze yield, reliability, power, timing, and variation impacts and develop Verilog simulation models.
  • Strong analytical, communication, documentation, collaboration, and independent execution skills.

Nice to have

  • Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
  • Experience in analog, full-custom, FPGA, ASIC, functional verification, or timing characterization.
  • Experience with dual-rail design, array biasing, sleep modes, power gating, and column-array multiplexing.
  • Experience with OCV timing and yield-variation analysis using Solido and Monte Carlo.

Culture & Benefits

  • Full-time employment within a global organization of approximately 17,000 employees.
  • Health benefits begin on the first day.
  • Retirement savings plans, restricted stock units, quarterly bonuses, and an employee stock purchase plan are offered.
  • Usual business hours with 0%–25% travel expected.
  • Career-development programs and a culture focused on trust, respect, diversity, communication, and employee development.

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