Senior Staff Engineer, Physical Design (ASIC)

TL;DR

Senior Staff Engineer, Physical Design (ASIC): Implementing complex integrated circuits and developing physical design methodologies for next-generation high-performance processor chips with an accent on RTL to GDS flows and design closure. Focus on implementing multi-voltage designs, optimizing physical verification, and automating productivity through scripting.

Location: Austin, TX

Salary: $155,000 - $185,000 per year

Company

hirify.global provides semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Perform physical implementation of complex integrated circuits (ICs).
• Develop and optimize physical design methodologies and RTL to GDS flows.
• Collaborate with Digital, RTL, and Analog teams to ensure design convergence and timely integration.
• Implement multi-voltage and low-power designs using place and route, static timing, and physical verification.
• Automate data extraction and productivity enhancements using Shell, Python, and TCL.
• Provide technical direction and mentoring to junior employees.

Requirements

• Master's degree in Computer Science, Electrical Engineering, or a related field.
• 3+ years of experience in backend physical design and physical verification.
• Proficiency in RTL to GDS flows and signoff design rule checking for advanced nodes.
• Expertise with Cadence Innovus and Synopsys Fusion Compiler tools.
• Experience with Verilog and multi-voltage/low-power design techniques.
• Must be eligible to access export-controlled information under U.S. law.

Culture & Benefits

• Competitive compensation and comprehensive benefits.
• Collaborative, transparent, and inclusive work environment.
• Provision of tools and resources to support professional growth and development.