Design Verification Engineer (AI Networking)

Location: San Jose, California, USA; onsite

Annual base salary: $120,000–$192,000

Company

hirify.global develops high-performance networking ASICs and multichip solutions, including Tomahawk products for scale-out and scale-up AI networks.

What you will do

• Verify L2/L3 network-switching and routing ASICs and chip subsystems.
• Analyze chip architecture and create test plans for traffic streaming, traffic management, scheduling, shaping, latency, and performance.
• Develop reusable verification environments, testbenches, verification APIs, scripts, and Makefiles.
• Implement test plans as executable test suites using SystemVerilog verification environments.
• Complete pre-silicon verification using functional and code coverage metrics.

Requirements

• BSEE, MSEE, PhD, or equivalent in digital design with strong academic performance.
• Typically 8+ years of engineering experience with a BS, 6+ years with an MS, or 3+ years with a PhD.
• Experience with Verilog, SystemVerilog, UVM, Perl, Python, and object-oriented programming.
• Experience with reusable object-oriented verification and validation environments.
• End-to-end ASIC or SoC verification experience, from test-plan definition through coverage closure on production silicon.
• Excellent verbal and written communication skills.

Culture & Benefits

• Discretionary annual bonus and new-hire and annual equity awards, subject to applicable plan documents.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Paid holidays, sick leave, vacation time, and applicable family and other leave benefits.
• Employee Assistance Program.