Design Verification Engineer (ASIC)

TL;DR

Design Verification Engineer (ASIC): Verifying cutting-edge network switch routing designs for AI networks with an accent on L2/L3 traffic streaming, traffic management, and performance characterization. Focus on implementing test plans into executable test suites using SystemVerilog and ensuring coverage closure for mass-production silicon.

Location: Onsite in San Jose, CA, USA

Salary: $120,000 - $192,000

Company

Global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Verify L2/L3 Network Switching and routing ASICs and various internal subsystems.
• Develop in-depth test plans for networking features, including traffic streaming, scheduling, shaping, and performance characterization.
• Build verification environments, including testbenches, verification APIs, scripts, and Makefiles.
• Implement test plans into executable test suites utilizing a SystemVerilog verification environment.
• Execute the pre-silicon verification process to completion using functional and code coverage metrics.

Requirements

• MSEE, BSEE, or equivalent degree with a concentration in digital design.
• Experience level: BS + 8+ years, MS + 6+ years, or PhD + 3+ years of engineering experience.
• Proficiency in Hardware Description Languages (Verilog, SystemVerilog, UVM), scripting (Perl, Python), and OOP.
• Proven experience in end-to-end verification from test plan definition to coverage closure for mass-produced ASIC/SOC silicon.
• Excellent verbal and written communication skills.
• Must be based in the USA

Culture & Benefits

• Competitive base salary with discretionary annual bonuses and equity grants.
• Comprehensive medical, dental, and vision insurance plans.
• 401(K) participation with company matching and Employee Stock Purchase Program (ESPP).
• Company-paid holidays, paid sick leave, and vacation time.
• Support for family leave and other legal leaves of absence.