R&D Engineer Physical Design (ASIC)

TL;DR

R&D Engineer Physical Design (ASIC): Delivering cutting-edge CMOS ASICs for AI/ML, networking, and computing applications with an accent on physical design implementation and chip-level integration. Focus on addressing complex challenges in timing closure, signal integrity, and power-area-performance trade-offs from concept to tapeout.

Location: Must be based in San Jose, CA, USA

Salary: $143,800 - $230,000

Company

hirify.global develops critical infrastructure chips that empower customers across nearly every major segment of the semiconductor industry.

What you will do

• Communicate directly with customers regarding design requirements.
• Integrate hirify.global IPs, memories, SerDes, and I/O subsystems.
• Manage chip-level planning, place and route, and physical verification.
• Address complex challenges in timing closure and signal integrity.
• Evaluate design trade-offs involving power, area, and performance.
• Execute timing analysis for both mission and test modes.

Requirements

• BS in Electrical Engineering with 12+ years of experience or MS with 10+ years of experience.
• Proven expertise in physical ASIC design and tapeout processes.
• Strong understanding of clocking architectures and test structure integration.
• Ability to work on-site in San Jose, CA.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Competitive new hire equity grant and annual equity awards.
• Employee Stock Purchase Program (ESPP).
• Paid holidays, sick leave, and vacation time.