R&D Engineer IC Design (ASIC)

TL;DR

R&D Engineer IC Design (ASIC): Designing and verifying front-end design blocks for cores with an accent on architecture definition, logic design, and synthesis. Focus on timing analysis, formal verification, and executing the complete ASIC implementation flow from RTL to closure.

Location: USA-TX-Austin

Salary: $121,900–$195,000

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Perform front-end design and verification of core design blocks.
• Define architecture, develop logic design, and handle synthesis and constraint development.
• Conduct design verification through simulation and formal verification.
• Analyze timing from physical implementation and debug designs using Verilog simulation.
• Work with the complete ASIC design and implementation flow from RTL synthesis to timing closure.

Requirements

• BS/MS in Electrical or Computer Engineering or equivalent.
• Bachelors with 8+ years of related experience or Masters with 6+ years of related experience.
• Proficiency with TCL/Perl scripting and synthesis tools (Synopsys Design Compiler/DC topo or Cadence RTL compiler).
• Experience with Primetime for timing analysis in high-frequency designs and advanced technology nodes.
• Knowledge of liberty LIB models and formal verification tools (Synopsys Formality / Cadence Conformal).
• Experience with Spyglass Lint, power analysis of RTL/gate level netlists, and DFT/scan methodology.

Culture & Benefits

• Competitive annual base salary with discretionary annual bonuses.
• New hire equity grants and annual equity awards.
• Comprehensive medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Paid sick leave, vacation time, and company-paid holidays.