обновлено 5 дней назад
Senior Custom ASIC Engineering Lead (ASIC)
143 800 - 230 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Custom ASIC Engineering Lead (ASIC): Leading customer ASIC programs from RFQs and technology collateral through design, testing, packaging, fabrication, bring-up, and production with an accent on physical design, STA, DFT, packaging, and tape-out quality. Focus on analyzing PPA tradeoffs, identifying design and schedule risks, executing EDA flows, and coordinating cross-functional engineering teams across AI, HPC, networking, and storage chips.
Location: San Jose, California, USA
Annual base salary: USD 143,800–230,000
Company
develops infrastructure chips that enable customers to produce custom ASICs for semiconductor industry applications, including AI, HPC, networking, and storage.
What you will do
- Manage external customer ASIC programs from RFQs through technology and IP collateral, design, testing, packaging, fabrication, bring-up, and production.
- Advise customer teams on EDA tools, design flows, methodologies, and best practices.
- Assess design-quality and schedule risks and coordinate mitigation actions with cross-functional teams.
- Execute physical design flows to verify that customer tape-in netlists meet tape-out quality standards.
- Coordinate technical discussions with experts and collaborate with marketing, sales, legal, and regulatory compliance teams.
- Share technical findings and support other engineering teams when needed.
Requirements
- Multiple tape-outs in advanced technology nodes.
- 12+ years of related experience with a bachelor's degree, or 10+ years with a master's degree.
- Experience analyzing PPA tradeoffs across library components and architectures.
- Knowledge of low-power design and power management.
- Hands-on experience with physical design, STA, EDA tools, logic simulation, testing, packaging, and related design flows.
- Programming experience with TCL, shell, and scripting languages.
Nice to have
- Exposure to SERDES communication protocols.
- Experience with logic design, chip architecture, microarchitecture, Verilog RTL, front-end logic design verification, DRC, or logic synthesis.
- Knowledge of DFT methods, including scan, memory BIST, and repair.
Culture & Benefits
- Collaboration with internal and external cross-functional engineering teams.
- Discretionary annual bonus and competitive new-hire and annual equity awards.
- Medical, dental, and vision plans.
- 401(k) participation with company matching and an Employee Stock Purchase Program.
- Paid holidays, sick leave, vacation time, and applicable family and other leaves of absence.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
12 дней назад
RTL2GDS IC Sr. Principal Design Engineer (Digital Implementation)
161 000 - 299 000$
6 дней назад
Senior DFT Logic Design Engineer (ASIC)
141 910 - 269 100$
10 дней назад
Principal Physical Design Engineer (ASIC/SoC)
180 000 - 260 000$
6 дней назад
Senior Staff ASIC Platform Engineer
150 000 - 255 000$
6 дней назад
Principal Digital Design Engineer (AI Infrastructure)
185 000 - 230 000$
9 дней назад
Technical Chief of Staff for ASIC Engineering (AI Infrastructure)
216 000 - 300 000$