Principal Physical Design Engineer (ASIC/SoC)

Location: Remote

Salary: $180,000–$260,000 per year, plus equity, benefits, and 401(k)

Company

hirify.global develops complex semiconductor and ASIC/SoC designs.

What you will do

• Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff.
• Develop floorplans and implementation strategies covering hierarchy, macros, congestion, timing, power, and routability.
• Drive placement, optimization, clock-tree synthesis, routing, extraction, timing closure, ECOs, and top-level timing convergence.
• Lead physical verification and power-integrity activities, including DRC, LVS, antenna, density, connectivity, IR drop, and electromigration analysis.
• Partner with RTL, architecture, DFT, verification, package, SI/PI, and other engineering teams to resolve cross-functional design issues.
• Improve physical design flows, scripts, automation, metrics, and methodologies while mentoring other engineers.

Requirements

• 10+ years of ASIC or SoC physical design experience with multiple successful tapeouts.
• Expertise in floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification.
• Strong experience with static timing analysis, multi-mode multi-corner timing closure, clock design, variation, extraction, power delivery, IR drop, electromigration, and signal integrity.
• Experience with Cadence and/or Synopsys physical implementation and signoff tools.
• Strong scripting and automation skills using Tcl, Python, Perl, or similar languages.
• Ability to independently drive complex technical problems to closure and provide technical leadership without formal management authority.

Nice to have

• Experience with advanced process nodes and large, high-frequency, or highly interconnected semiconductor designs.
• Experience with hierarchical design, top-level physical integration, physical design methodologies, and automation.
• Experience with multi-die, chiplet, or advanced packaging architectures.
• Experience in an early-stage semiconductor environment and familiarity with EDA tool evaluation and benchmarking.

Culture & Benefits

• Remote position within a highly collaborative, fast-paced engineering organization.
• Opportunity to join as an early member of the physical design team.
• Meaningful equity, benefits, and 401(k).
• Technical mentorship, design reviews, methodology reviews, and tapeout readiness work.