Design Verification (Staff To Senior Staff Engineer) (ASIC)

TL;DR

Design Verification (Staff To Senior Staff Engineer) (ASIC): Developing and implementing verification plans for read channel storage IP designs with an accent on functional and performance verification. Focus on creating complex testbenches using UVM and SystemVerilog to identify and resolve design issues in custom SoC for cloud data centers.

Location: Ho Chi Minh, Vietnam

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Develop and implement verification plans for read channel storage IP designs.
• Create and maintain testbenches using industry-standard verification tools and UVM.
• Perform functional and performance verification of complex digital designs.
• Collaborate with design and architecture teams to resolve design issues.
• Analyze and debug simulation failures and provide detailed verification reports.
• Mentor and guide junior verification engineers.

Requirements

• BS/MS/PhD Degree in Electrical Engineering, Computer Engineering, or related field.
• Proficiency in SystemVerilog, UVM, and scripting languages like Python or Perl.
• Strong understanding of ASIC design flow and digital verification methodologies.
• Experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics).
• Knowledge of Digital Signal Processing (DSP) and DSP modeling in C/C++.
• English: Fluent communication skills required.

Culture & Benefits

• Competitive salary, 13th-month salary, and performance-based bonuses.
• RSU grants for new joiners and ongoing annual awards.
• Premium health and accident insurance for employees and their families.
• Generous leave policy: 15 annual days, 3 company-wide recharge periods, and 5 sick days.
• Annual medical check-ups and various team-building events (trips, sports tournaments, etc.).