IC Layout Engineer (Mixed-Signal)

TL;DR

IC Layout Engineer (Mixed-Signal): Executing high-quality layouts for Standard Cells, I/O pads, and Mixed-Signal IP in advanced semiconductor processes with an accent on high-performance and robust layout design. Focus on managing layouts from the transistor level up, cell- and block-level floorplanning, and physical verification using advanced nodes.

Location: Singapore (Yishun)

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Execute high-quality layouts for Standard Cells, I/O pads, and Mixed-Signal IP.
• Apply design guidelines and advanced process rules to ensure robust and high-performance layouts.
• Manage layout execution from the transistor level up, including cell- and block-level floorplanning.
• Collaborate with engineers across multiple sites to adopt emerging layout methodologies and innovations.

Requirements

• Bachelor's degree in Electronic Engineering.
• 3 to 4+ years of hands-on IC layout experience.
• Expertise in Standard Cell, Memory, Full Custom, and/or Analog/Mixed-Signal layout.
• Deep understanding of advanced nodes (e.g., 5nm, 3nm, 2nm, 1.4nm).
• Proficiency with Cadence Virtuoso and Calibre for physical verification (DRC, LVS, ERC, Antenna, EM/IR).
• Solid understanding of ESD and Latch-up principles for I/O design.

Nice to have

• Scripting knowledge in Shell, Python, or Tcl.
• Experience with Cadence SKILL programming.

Culture & Benefits

• Equal opportunity employer focusing on diversity and inclusion.
• Collaborative team environment with opportunities to work on cutting-edge semiconductor technology.
• Professional growth within a leading global corporation.