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4 часа назад

Analog Layout Engineer (RF)

97 700 - 203 800$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR

Analog Layout Engineer (RF) (Analog and mixed-signal semiconductor design): Developing block-level and IP-level layouts for advanced semiconductor nodes with an accent on RF, FinFET, deep sub-micron, and high-speed circuit design. Focus on floorplanning, top-level integration, resolving complex DRC/LVS issues, and applying EM, ESD, antenna, latch-up, and reliability expertise through tape-out.

Location: Onsite in Santa Clara, California, United States

Salary: $97,700–$203,800 base compensation annually, plus potential variable compensation.

Company

hirify.global is an engineering services and technology transformation company providing R&D and software engineering solutions to organizations across more than 50 countries.

What you will do

  • Develop block-level and IP-level analog and RF layouts from concept through tape-out.
  • Own floorplanning, placement, routing, and optimization for SerDes, ADC/DAC, PLL, and other complex mixed-signal blocks.
  • Lead and support top-level integration of analog and mixed-signal blocks into larger SoCs.
  • Apply deep sub-micron and FinFET expertise, including fabrication, EM, ESD, latch-up, antenna, and reliability considerations.
  • Resolve DRC, LVS, antenna, and verification issues while collaborating with circuit designers and global layout teams.
  • Mentor and guide team members as a technical lead.

Requirements

  • Bachelor’s degree in Electrical Engineering, Electronics, or a related field.
  • At least 6 years of hands-on analog and/or RF layout design experience; 8 or more years preferred.
  • Experience with analog floorplanning and layout for SerDes, ADC/DAC, PLL, and similar high-speed or precision circuits.
  • Strong understanding of analog layout best practices for deep sub-micron CMOS and FinFET technologies.
  • Ability to work onsite in Santa Clara and collaborate across global engineering teams.

Culture & Benefits

  • Collaborative global engineering and layout organization.
  • Paid time off, company holidays, personal days, and sick leave.
  • Medical, dental, and vision coverage.
  • Retirement savings plan, life and disability insurance, and employee assistance programs.
  • Additional benefits are provided according to local policy and eligibility.

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