Senior Staff Digital Design Engineer (ASIC)

TL;DR

Senior Staff Digital Design Engineer (ASIC): Developing high-performance connectivity silicon for AI scale data centers with an accent on advanced digital pipelines and high-speed datapaths. Focus on implementing complex ASICs integrating DSP algorithms and Ethernet protocols to enable ultra-high bandwidth data movement.

Location: Irvine, CA (Onsite)

Salary: $135,900 - $201,130 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Collaborate with systems and architecture teams to define SoC-level specifications regarding performance, power, and DSP considerations.
• Translate product and protocol requirements into detailed micro-architecture for high-speed datapaths and DSP pipelines.
• Own RTL development using SystemVerilog to deliver high-quality, synthesizable logic meeting performance targets.
• Implement the full ASIC front-end design flow, including lint, CDC/RDC, synthesis, and timing constraint development.
• Partner with STA and PNR teams to support timing closure and design optimization on advanced process nodes (5nm, 3nm).
• Drive post-silicon bring-up and debug in collaboration with lab and systems teams.

Requirements

• 10+ years of industry experience working on large-scale ASICs for networking or data-center connectivity.
• Strong background in high-performance DSP and high-speed datapath design.
• Proficiency with front-end design flows, including synthesis, STA, and power/performance optimization.
• Familiarity with Ethernet protocols and networking standards (MAC, PCS framing, flow control).
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).
• BS/MS in Electrical Engineering, Computer Engineering, or a related field.

Nice to have

• Advanced high-speed DSP algorithm implementation (FFE, DFE, CTLE).
• Experience with FEC architectures such as LDPC, RS, or BCH.
• Previous PHY design experience, including PMA-level DSP pipelines and SerDes-adjacent logic.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive financial well-being and family support programs.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate professional milestones.