R&D Engineer IC Design (Semiconductors)

TL;DR

R&D Engineer IC Design (SystemVerilog/UVM): Verification of complex switch designs with an accent on creating verification environments and executing testplans for RTL and gatesim-based designs. Focus on developing testbenches, checkers, transactors, and C-based diagnostic tests for actual silicon.

Location: San Jose, CA, USA

Salary: $120,000 - $192,000

Company

A global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Perform verification of complex switch designs.
• Create SystemVerilog-based verification environments, including testbenches, checkers, and transactors.
• Develop and execute testplans for RTL and gatesim-based designs at both block and chip levels.
• Create ATE testing vectors for hardware validation.
• Develop C-based diagnostic tests to be executed on actual silicon.

Requirements

• Master's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent.
• Minimum of 6 years of work experience in Design Verification.
• Strong hands-on experience with verification methods, tools, and environments.
• Proficiency in SystemVerilog and scripting languages.
• Must be authorized to work in the USA.

Nice to have

• Knowledge and experience with UVM methodology.
• Knowledge of networking and switching concepts.

Culture & Benefits

• Medical, dental, and vision insurance plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP) and equity awards.
• Paid sick leave, vacation time, and company paid holidays.
• Employee Assistance Program (EAP).