Digital Design RTL Engineer (SystemVerilog)

TL;DR

Digital Design RTL Engineer (SystemVerilog): Designing and delivering high-quality RTL for advanced process nodes (5nm and below) with an accent on PPA optimization, CDC, and RDC analysis. Focus on SoC integration, high-speed SerDes, and memory protocols (LPDDR/DDR/HBM) to ensure timing closure and successful physical design hand-off.

Location: Onsite in Fort Collins, Colorado, USA

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Develop high-quality SystemVerilog RTL for advanced process nodes (5nm and below).
• Execute PPA optimization, clock domain crossing (CDC), and Reset Domain crossing (RDC) analysis.
• Manage the full design lifecycle from initial specification through to timing closure and physical design hand-off.
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and meet project milestones.

Requirements

• BSEE required; MSEE or PhD preferred.
• 8+ years of industry experience.
• High proficiency in SystemVerilog.
• Experience with SoC integration, high-speed SerDes, LPDDR/DDR, and/or HBM protocols.
• Must be authorized to work in the USA.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(K) participation with company matching.
• Competitive new hire equity grants and annual equity awards.
• Employee Stock Purchase Program (ESPP).
• Paid sick leave, vacation time, and company-paid holidays.