Distinguished Engineer (Photonic Fabric)

TL;DR

Distinguished Engineer (Photonic Fabric): Owning the end-to-end development of heterogeneous photonic chiplets integrating high-speed electrical ICs and photonic integrated circuits with an accent on interconnect bandwidth and energy efficiency. Focus on designing micro-architecture, RTL development for SERDES, and ensuring seamless electrical-optical co-design for AI accelerators.

Location: Santa Clara, CA. Must be eligible to access export-controlled information as defined under U.S. export control laws (EAR).

Salary: $209,770 - $314,300 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Own end-to-end product design spanning Electrical IC, Photonic IC, firmware stack, and advanced packaging.
• Lead micro-architecture and RTL development for high-speed SERDES and digital subsystems (e.g., UALink, UCIe).
• Collaborate with verification teams to ensure robust functional and performance verification of electrical-optical interfaces.
• Drive DFT strategy for digital components, analog SERDES, and overall system-level testability.
• Partner with photonics teams to define PIC architecture and control schemes for robust co-design.
• Lead cross-functional teams through silicon bring-up, ATE enablement, and system-level validation.

Requirements

• Bachelor's degree with 15+ years of experience OR Master's/PhD with 8-12 years of professional experience in related fields.
• Deep expertise in ASIC/SoC development with a proven track record of end-to-end chip ownership.
• Strong experience in RTL design, high-speed analog SERDES, physical design, and manufacturing tests.
• Ability to articulate architectural tradeoffs regarding power, area, yield, and risk to executive leadership.
• Must be eligible to access export-controlled information per U.S. law.

Nice to have

• Prior experience delivering high-speed I/O or optical products into mass production.
• Previous experience as a Chip Lead, SoC Architect, or System-Level Technical Lead.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive financial well-being and family support programs.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate professional contributions.