Design Verification Engineer (SystemVerilog/UVM)

Location: San Jose, California, United States; fully on-site at an Arrow client office as requested by client leadership.

Company

hirify.global provides product engineering and semiconductor design services through eInfochips, supporting connected-product innovation and edge-to-cloud capabilities.

What you will do

• Develop and integrate verification testbench components, including BFM, drivers, monitors, and scoreboards.
• Create test plans and execute complete verification cycles for semiconductor and product-engineering designs.
• Perform stress and corner testing, failure debugging, gate-level simulations, assertions coding, and coverage closure.
• Use SystemVerilog HVL, SVTB/UVM, and C++ testbenches for design verification.
• Work with the team to complete verification closure and report progress to customers daily or weekly.
• Support customer satisfaction through effective technical communication and delivery.

Requirements

• 6+ years of experience in SystemVerilog HVL and C++/C.
• 6+ years of experience with UVM.
• Proficiency in verification debugging and assertions coding.
• Experience with Make, Perl, Python, or other scripting tools.
• Experience with any communication or hardware protocol.
• Ability to work fully on-site in San Jose and travel to an Arrow client office when requested.

Nice to have

• Understanding of DSP.
• Experience with Subversion and Bugzilla.

Culture & Benefits

• Medical, dental, and vision insurance.
• 401(k) with matching contributions.
• Short-term and long-term disability insurance.
• Health Savings Account and Health Reimbursement Account options.
• Paid time off, tuition reimbursement, and growth opportunities.