Senior Staff Design Engineer (Digital IC Design)

TL;DR

Senior Staff Design Engineer (Digital IC Design): Designing and developing high-speed digital IPs for customer computing, signal processing, and NAND flash controllers with an accent on RTL design, timing optimization, and silicon debugging. Focus on implementing complex digital architectures, ensuring timing closure, and conducting power analysis for data storage infrastructure.

Location: Santa Clara, CA. Applicants must be eligible to access export-controlled information as defined under applicable U.S. law.

Salary: $134,390 – $201,300 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Perform RTL design, verification, synthesis, and timing optimization for customer computing and NAND flash controller IPs.
• Conduct static timing checks, CDC checks, Lint checks, and power analysis.
• Execute design reviews and lead silicon debugging efforts.
• Develop and maintain comprehensive design documentation and support user specifications.
• Collaborate within a specialized group of engineers to build high-speed digital IPs.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 10+ years of experience in digital IC design.
• Proficiency in RTL design using System Verilog.
• Expertise in timing closure, power analysis, and CDC checks.
• Ability to apply architecture-level thinking to complex sub-systems.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate professional contributions.