Physical Design Engineer (AI/ML)

TL;DR

Physical Design Engineer (AI/ML): Designing and executing the physical implementation of PCIe Switch and Enterprise Storage products for next-generation AI/ML ecosystems with an accent on RTL-to-silicon tape-out and timing closure. Focus on synthesis, physical verification, and managing complex clock tree synthesis and floor-planning for mega datacenters.

Location: Must work in person at the Colorado Springs site - no remote work allowed

Salary: USD 129,400.00 - 207,000.00

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions, focusing on high-performance data center and AI/ML ecosystems.

What you will do

• Execute the full physical design cycle from RTL to silicon tape-out.
• Perform synthesis, physical verification, and timing closure using advanced strategies and top-level STA.
• Conduct EM/IR analysis, place and route, and top-level floor-planning.
• Develop and optimize clock tree synthesis, focusing on insertion reduction and skew balancing.
• Develop design flows and methodologies in collaboration with IC Design RTL Engineers.

Requirements

• Bachelor’s degree in Electrical Engineering or Electronics Engineering.
• 12+ years of relevant experience in physical IC design.
• Proficiency in EDA tools and scripting languages including TCL and PERL.
• Proven experience managing the full physical design cycle from RTL to Tape-out.
• Excellent verbal and written communication skills.

Culture & Benefits

• Competitive base salary with discretionary annual bonuses and equity grants.
• Comprehensive health package including medical, dental, and vision plans.
• 401(K) participation with company matching and Employee Stock Purchase Program (ESPP).
• Paid sick leave, vacation time, and company-paid holidays.
• Access to the Employee Assistance Program (EAP).