STA Engineer (ASIC)

TL;DR

STA Engineer (ASIC): Designing and manufacturing next-generation high-performance, power-efficient ASICs with an accent on timing closure and analysis. Focus on debugging constraints, creating timing ECOs, and implementing timing infrastructure to ensure system reliability.

Location: Onsite in Fort Collins, Colorado, USA

Salary: USD 129,400 - 207,000

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Manage all aspects of timing closure for high-performance ASICs.
• Collaborate with design and physical design teams to debug constraints and facilitate logic changes.
• Create timing ECOs for project tapeouts.
• Develop and maintain scripts and methodologies for timing analysis and runs.
• Perform deep analysis of timing paths to identify and resolve critical issues.
• Implement and document timing infrastructure and guidelines.

Requirements

• MSEE or equivalent degree required.
• 10+ years of relevant industry experience in STA.
• Experience with large high-performance SoC designs in sub-micron technologies.
• Deep understanding of noise, cross-talk, OCV effects, and timing margin fundamentals.
• Proficiency in Perl and TCL programming.
• Familiarity with circuit modeling and SPICE models.

Culture & Benefits

• Annual base salary with discretionary annual bonus.
• Competitive new hire equity grants and annual equity awards.
• Comprehensive medical, dental, and vision plans.
• 401(K) with company matching and Employee Stock Purchase Program (ESPP).
• Paid sick leave, vacation time, and company-paid holidays.