Senior Engineer II - Design (ASIC)

Location: Hauppauge, New York, United States; onsite design role with 0–25% travel.

Annual base salary: $75,000–$205,000, plus restricted stock units and quarterly bonuses.

Company

hirify.global develops semiconductor products and connectivity solutions used in technologies around the world.

What you will do

• Contribute to the Networking and Communications Group Design Team.
• Design advanced connectivity devices, including Ethernet switches and bridges, USB hubs and power delivery solutions, PCIe bridges, and SerDes interfaces.
• Develop digital designs using Verilog and SystemVerilog.
• Work through ASIC design and verification flows.
• Simulate, debug, document, and support hardware development in a collaborative engineering environment.

Requirements

• Bachelor’s degree in Electrical Engineering or an equivalent engineering discipline.
• 7+ years of relevant industry experience.
• Experience with Ethernet, USB, and/or PCIe.
• Proficiency in Verilog and SystemVerilog.
• Experience with ASIC design and/or verification flows.
• Strong analytical, communication, documentation, problem-solving, debugging, and organizational skills.

Nice to have

• Knowledge of USB 3.0, USB 2.0, USB Power Delivery, PCIe, Ethernet, and 1G–25G SerDes protocols.
• Experience with SPI, I2C, UART, or similar peripheral interfaces.
• Experience with simulation tools and Xilinx FPGA emulation and debugging.

Culture & Benefits

• Collaborative environment focused on innovation, trust, empowerment, respect, diversity, and communication.
• Health benefits begin on the first day.
• Retirement savings plans and an employee stock purchase plan with a two-year look-back feature.
• Leadership and employee development programs.
• Physical work distribution includes approximately 80% sitting, 10% standing, and 10% walking.