Principal Physical Design Engineer (SoC)

Location: Austin (Oakhill, Office), United States

Company

hirify.global develops advanced semiconductor products and high-reliability SoCs.

What you will do

• Own end-to-end physical design execution from RTL through GDSII and silicon delivery.
• Lead floorplanning, synthesis, place and route, clock tree synthesis, routing, static timing analysis, power delivery network design, physical design verification, and signoff.
• Drive timing, power, IR/EM, physical verification, PPA, and tapeout closure for complex designs.
• Define next-generation physical design methodologies and optimize implementation flows and tools for advanced nodes.
• Mentor engineers, support career development, and provide execution status, escalation, and decision-making support to senior leadership.
• Collaborate with architecture, RTL, verification, product, EDA vendor, and IP provider teams, including support for post-silicon bring-up and production ramp.

Requirements

• Onsite work in Austin, United States.
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 10+ years of ASIC or SoC physical design experience.
• Expertise in full RTL-to-GDSII implementation using Synopsys and/or Cadence toolsets.
• Experience with floorplanning, synthesis, PNR, CTS, routing, STA, DRC/LVS/ERC, advanced-node implementation, and low-power design using UPF/CLP.
• Strong communication skills and scripting experience with Python, TCL, and Perl.

Nice to have

• Experience with high-reliability SoCs.
• Exposure to AI-driven design methodologies and automation.

Culture & Benefits

• Opportunity to own delivery of flagship SoCs at advanced technology nodes.
• Direct impact on silicon success and product competitiveness.
• Focus on innovation in physical design methodologies, automation, and flow optimization.
• Equal opportunity employment and reasonable accommodations for otherwise qualified disabled individuals.