IP Development Engineer (Hardware)

TL;DR

IP Development Engineer (Hardware): Developing and testing QA rulesets for memory compiler generated collateral with an accent on automation scripting and collateral quality analysis. Focus on building memory compiler specific checks, collaborating with design and QA teams, and ensuring high-quality memory deliverables.

Location: Hybrid (Austin, Texas). Not eligible for hirify.global immigration sponsorship.

Salary: $141,910.00 - $269,100.00 USD

Company

A global leader in semiconductor innovation and technology advancements.

What you will do

• Test and deploy QA rulesets to analyze and flag quality issues in memory compiler generated collateral.
• Act as a liaison between the design team and central QA team for the intake of the QA tool suite.
• Develop memory compiler specific checks to ensure high-quality deliverables.
• Provide first and second level support for the QA ruleset before escalation to vendors or central teams.
• Define necessary QA checks and establish capabilities in coordination with the central team.

Requirements

• MS degree with 7+ years or BS degree with 9+ years of experience in Electrical or Computer Engineering.
• Must be authorized to work in the US without sponsorship.
• 2+ years of experience in developing automation scripting.
• Familiarity with Hard IP deliverables and integration with vendors like Synopsys, Siemens, Ansys, and Cadence.

Nice to have

• PhD degree with 2+ years of experience in Electrical or Computer Engineering.
• Proficiency in Python, Perl, and/or Tcl.
• 5+ years of experience in IP circuit design.
• Experience with Siemens Solido crosscheck framework and Python unit tests.
• Experience with collateral types such as liberty, upf, rtl, avm, lef, oasis, or apache.

Culture & Benefits

• Competitive total compensation package including stock bonuses.
• Comprehensive health, retirement, and vacation programs.
• Hybrid work model allowing a split between on-site and off-site work.