обновлено 17 дней назад
Principal ASIC Physical Design Engineer (Space)
190 000 - 280 000$
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Principal ASIC Physical Design Engineer (Space): Leading end-to-end RTL-to-GDSII implementation of complex mixed-signal SoCs for next-generation satellite and space systems with an accent on timing closure, PPA optimization, advanced FinFET technologies, and package-aware integration. Focus on developing physical design methodologies, managing external design partners, solving multi-corner and multi-voltage implementation challenges, and supporting silicon bring-up through spaceflight.
Location: Seattle, Washington, United States
Salary: $190,000–$280,000 per year plus equity
Company
develops and mass-produces high-power satellite platforms for commercial and U.S. government missions from low Earth orbit to deep space.
What you will do
- Own the complete RTL-to-GDSII flow, including synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, physical verification, and sign-off.
- Develop physical design methodologies, scripts, and automation to optimize performance, power, and area.
- Drive timing closure across multiple voltage and process corners using foundry-qualified tools.
- Collaborate with architecture, RTL, DFT, verification, packaging, signal integrity, power integrity, and test teams on SoC and chip-to-board integration.
- Manage and technically guide external physical design partners, service vendors, and EDA vendors.
- Support chip bring-up, post-silicon debug, production, and spaceflight qualification.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of ASIC physical design experience for high-performance SoCs.
- End-to-end RTL-to-GDSII expertise with Synopsys, Cadence, or Siemens tools.
- Hands-on experience with timing closure, IR drop analysis, ECO implementation, multi-clock and multi-voltage SoCs, and hierarchical design.
- Experience with advanced FinFET process nodes, DFT integration, STA sign-off, and UPF/CPF power-domain implementation.
- Work involving ITAR-controlled information requires U.S. Person status or eligibility for a federally issued export-control license.
Nice to have
- Experience with radiation-hardened or space-qualified ASICs.
- Chip-package co-design, advanced 2.5D/3D packaging, or TSMC tapeouts.
- Experience with Gate-All-Around technologies.
- Experience coordinating offshore physical design teams and working in geographically distributed teams.
Culture & Benefits
- Collaborative, cross-functional design environment focused on rapidly developing large satellite platforms.
- Opportunity to contribute to SoCs that will fly in space.
- Comprehensive medical, dental, and vision coverage.
- Paid time off, paid parental leave, and life insurance.
- Equity in the company.
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