Назад
Company hidden
2 дня назад

Principal ASIC Physical Design Engineer (Aerospace)

190 000 - 280 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/

TL;DR

Principal ASIC Physical Design Engineer (Aerospace): Leading the implementation of complex SoCs for next-generation satellite systems with an accent on full RTL-to-GDSII flow ownership and advanced FinFET process nodes. Focus on achieving timing closure, optimizing PPA, and managing external design partners to ensure first-pass silicon success for space-qualified hardware.

Location: Must be based in Seattle, WA (Onsite). Role requires U.S. Person status due to ITAR export control regulations.

Salary: $190,000 – $280,000 + equity

Company

A Series C space startup building the largest and highest-power satellite platforms for missions from LEO to deep space.

What you will do

  • Own the complete RTL-to-GDSII flow including synthesis, floorplanning, place & route, and sign-off.
  • Develop and maintain physical design methodologies and automation to optimize PPA.
  • Collaborate with front-end, verification, and packaging teams to ensure efficient design iteration.
  • Drive timing closure across multiple voltage and process corners.
  • Manage and technically guide external physical design partners and service vendors.
  • Support chip bring-up, debug, and production integration for spaceflight hardware.

Requirements

  • Bachelor’s or Master’s degree in Electrical or Computer Engineering.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Must be a U.S. Person (citizen, green card holder, or protected individual) for ITAR compliance.
  • Proven expertise in RTL-to-GDSII flows using industry-standard tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Experience with advanced FinFET process nodes and managing outsourced PD teams.

Nice to have

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Experience driving tapeouts through TSMC.
  • Familiarity with Gate-All-Around technologies.

Culture & Benefits

  • Comprehensive benefits package including medical, dental, and vision coverage.
  • Paid time off and paid parental leave.
  • Equity participation in a high-growth space startup.
  • Collaborative environment focused on rapid manufacturing and space exploration.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →