Principal / Sr. Principal Digital Design Engineer (AI)

Location: San Jose, California, United States

Salary: $185,000–$230,000 per year, depending on experience, level, and business needs. Discretionary bonus, incentives, and benefits may be available.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for hyperscalers and ecosystem partners.

What you will do

• Architect and implement complex digital blocks and subsystems for high-performance AI connectivity products.
• Define micro-architecture and drive RTL implementation with optimized power, performance, and area trade-offs in advanced CMOS technologies.
• Lead timing closure, DFT implementation, functional verification, coverage closure, and gate-level simulation activities.
• Own third-party IP integration and block-level verification through sign-off.
• Drive designs through production and collaborate with post-silicon teams on silicon bring-up and debug.
• Mentor engineers and improve silicon development methodologies, CAD automation, and design infrastructure.

Requirements

• Bachelor’s degree in Electrical Engineering or an equivalent field.
• 10+ years of hands-on experience developing complex SoC or silicon products for server, storage, and/or networking markets.
• Expertise in architecture definition, micro-architecture, RTL coding, functional simulation, and synthesis.
• Strong knowledge of timing closure, gate-level simulation, DFT implementation, and Cadence and/or Synopsys digital design flows.
• Deep expertise in at least one high-speed protocol, such as PCIe, CXL, Ethernet, DDR, or a similar technology.
• Production experience with advanced CMOS nodes at 7nm or below.

Nice to have

• Master’s degree in Electrical Engineering or a related field.
• Experience delivering multiple high-performance designs to production in data-center environments.
• Experience collaborating with embedded firmware teams and knowledge of RISC-V, Arm, or similar processor subsystems.
• Contributions to design methodology, CAD automation, or design infrastructure.

Culture & Benefits

• Work on connectivity technologies supporting AI infrastructure and hyperscale deployments.
• Collaborate across design, verification, physical design, DFT, firmware, and post-silicon teams.
• Inclusive environment that encourages applications from people with diverse backgrounds and experiences.
• Potential eligibility for discretionary bonuses, incentives, and benefits.