Director, Design Verification (ASIC)

TL;DR

Director, Design Verification (ASIC): Leading design verification, emulation, and post-silicon validation for complex multi-chiplet SOCs with an accent on zero-defect execution and methodology definition. Focus on building high-performance engineering teams, driving test-bench architectures, and managing the product development cycle through successful tape-outs.

Location: Santa Clara, CA

Salary: $195,180 - $292,400 per annum

Company

A leading provider of semiconductor solutions for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Lead DV, emulation, and post-silicon validation execution with a zero-defect mindset.
• Define verification scope, execution timelines, and overall methodology strategies.
• Drive the definition and implementation of DV test-bench (TB) architectures.
• Collaborate with Architecture, Design, DFT, PD, and FW teams for successful product execution.
• Manage tool evaluation and drive continuous productivity improvements.
• Hire, build, and retain a high-performance engineering team.

Requirements

• 10-15 years of professional experience (or 5-10 with Master's/PhD) in Computer Science, Electrical Engineering, or related fields.
• Must be based in Santa Clara, CA.
• 10+ years of experience in block, sub-system, and SOC verification.
• Hands-on experience with verification methodologies and test-bench development.
• Proficiency in scripting languages such as Python, Perl, Tcl, and UNIX Shell.
• Must be eligible to access export-controlled information under U.S. law.

Culture & Benefits

• Employee stock purchase plan with a 2-year look-back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards for contributions and milestones.