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Mixed Signal Design Verification Engineer (VHDL/Verilog)

122 440 - 200 340$
Формат работы
hybrid
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Mixed Signal Design Verification Engineer (VHDL/Verilog): Developing functional verification plans, testbenches, simulation models, and verification environments for mixed-signal logic components with an accent on analog behavioral modeling, power and timing analysis, and presilicon debugging. Focus on identifying root causes of failing tests, implementing corrective measures, and improving verification infrastructure for complex architectural and microarchitectural features.

Location: Hybrid role with on-site work at an assigned hirify.global site in Hillsboro, Oregon, or Austin, Texas, United States.

Annual salary: $122,440–$200,340 USD.

Company

hirify.global designs and manufactures advanced silicon solutions and develops power delivery technology for digital products.

What you will do

  • Perform functional verification of mixed-signal logic components, including analog behavioral models, against specification requirements.
  • Develop IP verification plans, testbenches, verification environments, and coverage for mixed-signal microarchitecture specifications.
  • Execute verification plans and run system simulation models to verify designs, analyze power and timing, and uncover bugs.
  • Replicate, root-cause, and debug presilicon issues; implement corrective measures for failing tests.
  • Collaborate with digital and analog architects, RTL developers, and physical design teams to improve verification and meet functional, performance, and power goals.
  • Document test plans, lead technical reviews, and maintain and improve functional verification infrastructure and methodology.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of experience, or a master’s degree in one of these fields with 2+ years of experience.
  • Direct experience with digital logic.
  • Experience with VHDL, Verilog, and SystemVerilog.
  • Experience developing testbench components, preferably using OVM/UVM.
  • Design debugging skills.

Nice to have

  • 7+ years of related experience.
  • Analog debugging skills.
  • Real-number current and voltage simulation modeling and debugging skills.
  • Relevant experience gained through coursework, project work, internships, military training, or professional work.

Culture & Benefits

  • Hybrid work model combining on-site work at an assigned hirify.global location with off-site work.
  • Competitive compensation package with stock bonuses.
  • Health, retirement, and vacation benefits.
  • Shift 1 schedule in the United States of America.

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