R&D Engineer IC Design (SystemVerilog)

Location: San Jose, California, United States; onsite

Annual base salary: $120,000–$192,000

Company

hirify.global develops semiconductor and infrastructure technology products.

What you will do

• Verify complex switch designs at both block and chip level.
• Create SystemVerilog-based verification environments, including testbenches, checkers, and transactors.
• Create and execute test plans for RTL and gate-simulation-based designs.
• Create ATE testing vectors.
• Develop C-based diagnostic tests for execution on actual silicon.

Requirements

• Master’s degree in Electrical and Electronic Engineering, Computer Science, or an equivalent field.
• At least 6 years of work experience in design verification.
• Strong knowledge and hands-on experience with verification methods, tools, and environments.
• Strong programming skills, including SystemVerilog and scripting languages.

Nice to have

• Knowledge and experience with the UVM methodology.
• Knowledge and experience with networking and switching concepts.

Culture & Benefits

• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program and Employee Assistance Program.
• Company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leave.
• Eligibility for a discretionary annual bonus and equity according to applicable plan documents.