SSG Design Engineering Intern (Digital Design)

TL;DR

SSG Design Engineering Intern (Digital Design/Verification): Developing and verifying the Janus NoC IP product with an accent on RTL implementation and UVM-based verification. Focus on simulating and debugging RTL logic, running synthesis, and writing functional tests to achieve timing, area, and power goals.

Location: Must be based in San Jose, CA

Salary: $35/hr – $62/hr

Company

A world leader in computational software, semiconductor design IP, and system verification hardware.

What you will do

• Implement RTL for specified micro-architecture using System Verilog.
• Simulate and debug RTL logic and utilize EDA tools for synthesis, place & route to optimize timing, area, and power.
• Develop test plans and write functional tests (UVM) and verification monitors (SVA).
• Analyze coverage information and script Design Verification flows.
• Collaborate closely with Design, Verification, and Physical Design teams.

Requirements

• Currently enrolled in an MS or BS program majoring in Electrical Engineering, Computer Engineering, or a similar field.
• Deep understanding of Digital Design and/or Design Verification Fundamentals.
• Strong automation skills using Tcl, Perl, and shell scripting.
• Excellent oral and written communication skills.
• Location: Must be based in San Jose, CA; candidates from local schools are preferred.

Nice to have

• Exposure to design automation tools.

Culture & Benefits

• Opportunity to work at a global leader in semiconductor design IP.
• Eligibility for incentive compensation, including bonuses and equity.
• Access to professional development within a high-impact R&D environment.