Mixed Signal Logic Design Engineer (SystemVerilog)

Location: On-site in Hillsboro, OR; Phoenix, AZ; or Santa Clara, CA

Salary: $141,910–$269,100 USD

Company

hirify.global is a global leader in semiconductor innovation, focusing on scalable engineering solutions through its Central Engineering Group.

What you will do

• Develop architecture and microarchitecture specifications for logic components and contribute to system-level decisions.
• Implement specifications in RTL and lead junior designers in delivering complex logic blocks.
• Create behavioral models for analog and mixed-signal circuit blocks using SystemVerilog.
• Perform simulations and debugging using logic, mixed-signal validation, and AMS simulation tools.
• Collaborate with physical design and pre-silicon validation teams for synthesis, timing closure, and test plan development.
• Coordinate with post-silicon validation teams to resolve hardware issues.

Requirements

• BS in Electrical/Computer Engineering with 4+ years of experience, or MS with 3+ years.
• Proficiency in SystemVerilog and standard digital design concepts (e.g., FSM).
• Experience with computer architecture, analog design, ADC/DAC, and communications theory.
• Expertise in multiple clock-domain design and high-level architecture production.
• Must be based in or able to work on-site at the US locations mentioned.

Nice to have

• 10+ years (BS) or 8+ years (MS) of relevant professional experience.
• Knowledge of High-Speed I/O protocol stacks such as UCIe, PCIe, or USB.
• Proficiency in scripting languages like Python, Perl, or bash/csh.
• Experience with low-power design, power gating, and firmware development.
• Usage of AI tools as a productivity booster in the IP design process.

Culture & Benefits

• Competitive total compensation package including stock bonuses.
• Comprehensive health and retirement benefit programs.
• Paid vacation and industry-leading perks.
• Opportunity to work on cutting-edge high-speed mixed-signal IP designs.