Mixed Signal Logic Design Engineer (SystemVerilog)

TL;DR

Mixed Signal Logic Design Engineer (SystemVerilog): Developing high-speed mixed signal IP designs and logic components for chip integration with an accent on RTL implementation and behavioral modeling. Focus on optimizing power, performance, and area while ensuring design integrity through mixed-signal validation and AMS simulation.

Location: On-site presence required in Hillsboro (OR), Phoenix (AZ), or Santa Clara (CA), USA

Salary: $141,910.00 - $269,100.00 USD

Company

A global leader in semiconductor manufacturing and design, focusing on scalable engineering solutions for product and foundry businesses.

What you will do

• Develop architecture and microarchitecture specifications for logic components and overall system architecture decisions.
• Implement designs in RTL and coordinate with junior designers to deliver high-quality, complex logic blocks.
• Create behavioral models for analog and mixed-signal circuit blocks using SystemVerilog.
• Conduct simulations and debugging using mixed-signal validation and AMS simulation tools.
• Collaborate with physical design teams to ensure synthesis and timing closure.
• Partner with pre- and post-silicon validation teams to develop test plans and resolve hardware issues.

Requirements

• BS degree in Electrical/Computer Engineering with 4+ years of experience, or an MS degree with 3+ years of experience.
• Must be based in or able to work on-site in the USA.
• Proficiency in SystemVerilog and standard digital design concepts, including FSM design techniques.
• Experience with computer architecture, analog design, ADC/DAC designs, and communications theory.
• Capability to produce high-level architecture meeting industry-standard specifications.
• Experience with multiple clock-domain design.

Nice to have

• 10+ years (BS) or 8+ years (MS) of relevant experience with a track record of guiding junior designers.
• Knowledge of High-Speed I/O protocol stacks (UCIe, PCIe, USB, etc.).
• Proficiency in scripting languages such as Python, Perl, or bash/csh.
• Experience with low-power design, power gating, and multiple power-domain design.
• Experience leveraging AI tools to improve productivity in the IP design process.

Culture & Benefits

• Competitive total compensation package including stock bonuses.
• Comprehensive benefits programs covering health, retirement, and vacation.
• Opportunity to work at the forefront of silicon innovation within the Central Engineering Group.