Physical IC Design Engineer (AI/ML)

TL;DR

Physical IC Design Engineer (AI/ML): Execution of chip-level physical verification for advanced nodes to drive AI and ML ecosystems with an accent on DRC, LVS, and DFM. Focus on developing verification methodologies, resolving integration issues, and optimizing runtime flows for silicon tape-out.

Location: Must work in person at the San Jose site; no remote work allowed

Company

hirify.global is a leading global provider of semiconductor and infrastructure software solutions.

What you will do

• Execute chip-level physical verification and resolve complex issues.
• Set up runsets for advanced nodes and tool flows.
• Manage and guide rules for top-level floorplan, I/O, and bump planning.
• Provide technical direction on verification methodologies, including DRC, LVS, ERC, and PERC.
• Develop best practice guidelines for physical verification flows and runtime optimizations.
• Collaborate with the physical design team to resolve critical top-level integration violations.

Requirements

• Bachelor's degree in Electrical Engineering (8+ years exp) or Master's (6+ years exp) in physical design and verification.
• Hands-on experience running physical verification (LVS, DRC, ERC, PERC).
• Proficiency with EDA tools such as ICV, Calibre, and Pegasus.
• Experience with parasitic extraction tools like StarRC or Quantus.
• Ability to script in Python, Tcl, or Perl.
• Must be based in San Jose, CA; strictly onsite role with no remote work.

Nice to have

• Rule deck coding experience in ICV, Calibre, or Pegasus.
• Experience analyzing ESD, latch-up, and power-domain isolation vulnerabilities (ERC/PERC).
• Knowledge of Yield Enhancement (DFM), critical area analysis (CAA), and via-doubling.

Culture & Benefits

• Comprehensive medical, dental, and vision plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP) and equity awards.
• Discretionary annual bonus.
• Paid sick leave, vacation time, and company paid holidays.