ASIC Implementation Engineer STA

Location: San Jose, California, United States

Annual base salary: USD 143,800–230,000, plus a discretionary annual bonus and equity awards.

Company

hirify.global develops semiconductor and technology solutions, with this role focused on ASIC implementation and sign-off.

What you will do

• Own full-chip static timing sign-off and final timing closure across process, voltage, and temperature corners.
• Author, validate, and maintain SDC constraints for functional and test modes, including Scan, MBIST, and ATPG.
• Incorporate foundry guidelines, sign-off corners, margins, and derates into timing-analysis flows.
• Manage multi-mode multi-corner analysis across hundreds of timing scenarios.
• Automate and implement timing ECOs to resolve setup, hold, and transition violations.
• Partner with RTL, Physical Design, and DFT teams on timing issues, guard-banding, and power, performance, and area trade-offs.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering.
• At least 12 years of hands-on experience in ASIC STA, timing-constraint development, and timing closure.
• Experience with Cadence or Synopsys sign-off tools and industry-standard EDA tools.
• Deep knowledge of AOCV/POCV, crosstalk, IR-drop-aware STA, and MMMC constraints.
• Strong proficiency in Tcl and experience with Python, Perl, or shell scripting.
• Strong problem-solving, communication, and collaboration skills.

Culture & Benefits

• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program and Employee Assistance Program.
• Company-paid holidays, paid sick leave, vacation time, and applicable paid family leave.
• Annual bonus opportunity, competitive new-hire equity, and annual equity awards.