Transmitter (Tx) SerDes Design Lead (224G/448G)

TL;DR

Transmitter (Tx) SerDes Design Lead (224G/448G): Own schematic-level design and post-layout verification of high-speed electrical transmitter macros for 224G and 448G SerDes in deep-submicron CMOS, with an accent on transmitter signal-chain architecture, extraction-based simulation, and silicon correlation. Focus on solving complex performance gaps across bandwidth, linearity/return loss, jitter, and power under process/voltage/temperature variation.

Location: Ottawa

Salary: $138,000 - $220,400 CAD (annual)

Company

hirify.global develops high-speed optical transmission solutions for modern telecommunications networks.

What you will do

• Own schematic-level design and post-layout verification of the transmitter signal chain blocks: DAC-based output stage, serialization, clocking interface, and output driver.
• Evolve transmitter architecture with system designers and lab validation teams to meet standard and product requirements.
• Evaluate circuit topologies and recommend implementations balancing power, area, bandwidth, and technology constraints.
• Deliver designs through full GDSII integration by collaborating with layout and design engineers.
• Drive extraction-based post-layout simulations and validate transmitter performance (bandwidth, linearity/RLM, return loss, jitter, and power) across PVT corners.
• Perform root-cause analysis for design and post-layout performance gaps and implement corrective design actions; maintain block- and transmitter-level performance/power tracking.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering, or an applicable scientific discipline.
• 10+ years of industrial experience designing high-speed analog, mixed-signal, or SerDes transmitter circuits in advanced CMOS technologies, from schematic design through post-layout verification.
• Experience with transmitter building blocks: DAC-based output stages, serializers/multiplexers, output drivers, and clocking circuits.
• Proven ability to execute post-layout and extraction-based simulations to validate performance across process, voltage, and temperature conditions.
• Experience delivering analog circuit designs through silicon validation.
• Hands-on use of Cadence, Mentor, or Synopsys tools (Virtuoso, Calibre, STAR-RC, MMSIM) and strong written/verbal communication with ability to work independently and in a team.

Nice to have

• Experience with 224G or 448G PAM4/PAM6 SerDes and related OIF-CEI or IEEE standards.
• Experience contributing to transmitter architecture using MATLAB, Verilog-A, or C++.
• Experience with signal integrity/power integrity/channel/package co-design and EM tools such as HFSS or EMX.
• Experience mentoring engineers within analog macro design teams.
• Experience with mixed-signal validation using high-speed measurement and probing equipment.

Culture & Benefits

• Comprehensive benefits package including medical, dental, and vision plans.
• Retirement savings participation: 401(K) (USA) & DCPP (Canada) with company matching.
• Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), paid sick leave, and vacation time.
• Company-paid holidays and support for paid family leave and other leaves of absence.
• People-first culture with emphasis on flexibility, growth, well-being, and belonging.

Hiring process

• Interviews to assess technical depth in SerDes transmitter design, simulation/verification, and silicon validation.
• Discussion of experience with relevant tools, standards, and performance tradeoffs.