Analog/Mixed Signal Verilog Modeling Design Engineer

TL;DR

Analog/Mixed Signal Verilog Modeling Design Engineer (Embedded/Chip Design): Developing Digital-Mixed Signal (DMS) models for analog IPs like touch controllers and health sensing AFEs with an accent on SystemVerilog, Verilog-AMS, and chip verification. Focus on understanding analog circuits, RTL design, and leveraging AI tools for model generation.

Location: Onsite in Irvine, CA or San Jose, CA, USA

Salary: $120,000–$192,000 annually

Company

hirify.global is a global technology leader designing, developing, and supplying a broad range of semiconductor and infrastructure software solutions.

What you will do

• Develop Digital-Mixed Signal (DMS) models for analog IPs using SystemVerilog language.
• Interface with analog design and chip DV teams to develop and support models for chip verification.

Requirements

• Experience: Bachelor's degree and 8+ years of related experience.
• Good knowledge of Verilog-AMS modeling language and SystemVerilog UDT/UDR nettype.
• Familiarity with analog circuits such as LDOs, TIAs, analog muxing, and SARADC.
• Understand good coding of RTL of digital design and testbench creation.
• Fully familiar with SV .vs. schematic verification for a given leaf SV model.
• Familiar with Cadence linting and simulation tools (ncsim, xrun, vcs) and analog schematic editor.
• Hands-on skills in scripting languages (TCL, Perl, Python).

Nice to have

• Experience with using AI tools such as Cursor or chipAgents to generate analog SV models and testbenches based on design specifications.

Culture & Benefits

• Competitive and comprehensive benefits package.
• Medical, dental, and vision plans.
• 401(K) participation including company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company paid holidays, paid sick leave, and vacation time.