Analog/Mixed Signal Verilog Modeling Design Engineer (SystemVerilog)

Location: USA-CA Irvine Alton Parkway Bldg 1

Company

hirify.global develops semiconductor and connectivity technologies.

What you will do

• Develop digital-mixed-signal models of analog IPs, including touch controller AFEs, wireless power charging, health sensing AFEs, and satellite AFEs.
• Use SystemVerilog to create and support analog/mixed-signal models for chip verification.
• Collaborate with analog design and chip design verification teams.
• Run SystemVerilog versus schematic verification for leaf SV models.
• Create digital RTL and testbenches for functions such as clock dividers, decoders, and finite-state machines.
• Use scripting and AI tools to generate analog SV models and testbenches from design specifications.

Requirements

• Bachelor’s degree and 8+ years of related experience.
• Strong knowledge of SystemVerilog, including UDT/UDR nettypes with Cadence wreal or EEnet packages.
• Understanding of Verilog-AMS modeling.
• Experience with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample-and-hold circuits, comparators, DAC voltage converters, buffering, and amplification.
• Familiarity with Cadence linting and simulation tools, including ncsim, xrun, and vcs, as well as analog schematic editors.
• Hands-on scripting experience with TCL, Perl, or Python.

Culture & Benefits

• Full-time employment with a discretionary annual bonus.
• Competitive new-hire and annual equity awards, subject to applicable plan documents.
• Medical, dental, and vision coverage.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Employee Assistance Program, paid holidays, paid sick leave, vacation, and applicable family and other leave.
• Equal opportunity employment in accordance with applicable laws.